1. Field of the Invention
The present invention relates to a semiconductor device having a metal interconnection.
2. Description of the Related Art
Some of known conventional semiconductor devices are disclosed in U.S. patent application Ser. Nos. 4,789,648 and 4,944,836. The first conventional semiconductor device will be described with reference to FIGS. 1A and 1B and the second conventional semiconductor device will be described with reference to FIGS. 2A to 2E.
(a) First Conventional Semiconductor Devices
First, the semiconductor device described in U.S. patent application Ser. No. 4,789,648 (hereinafter called the "first prior art example") will be discussed with reference to FIGS. 1A and 1B. FIGS. 1A and 1B are vertical crosssectional views illustrating the fabrication process for this semiconductor device (first prior art example) consisting of steps 1A and 1B.
According to the first prior art example, as shown in FIG. 1A, an insulating film 104a as a silicon dioxide film is formed on a silicon substrate 101 by chemical vapor deposition (hereinafter referred as CVD) or the like, a groove pattern is formed by known techniques, and then an aluminum film (Al film) 114 as a conductive film is formed by sputtering.
At this time, the thickness of the insulating film 104a is set equal to the thickness of the necessary interconnection film plus the thickness of the conductive film. A silicon nitride which serves as a stopper at the later step of polishing the metal film may be formed on the insulating film 104a.
Subsequently, the Al film 114 is polished and removed by chemical-mechanical polishing (hereinafter called "CMP") using a slurry consisting of alumina (Al.sub.2 O.sub.3)-added deionized water or an Al.sub.2 O.sub.3 -added nitrate solution, yielding a groove interconnection structure which has a groove pattern filled with an interconnection material (Al film 114), as shown in FIG. 1B.
(b) Second Conventional Semiconductor Devices
Next, the semiconductor device described in U.S. patent application Ser. No. 4,944,836 (hereinafter called the "second prior art example") will be discussed with reference to FIGS. 2A to 2E. FIGS. 2A-2E are vertical cross-sectional views illustrating the fabrication process for this semiconductor device (second prior art example) consisting of steps A to E.
According to the second prior art example, as shown in FIG. 2A, an insulating film 104a and an underlying Al interconnection 112 are formed using known techniques, an insulating film 104b (which may be a silicon dioxide film) is formed on the surface of the resultant structure, and a stopper 113 of Al.sub.2 O.sub.3 is then formed in a predetermined region by lithography, etching and the like.
Then, an insulating film 104c as a silicon dioxide film is formed on the stopper 113 and the insulating film 104b, as shown in FIG. 2B.
Next, as shown in FIG. 2C, the insulating film 104c and insulating film 104b are patterned by selective etching using a resist (not shown) as a mask to form an interlayer contact hole 105 which reaches the underlying Al interconnection 112.
As the stopper 113 is not etched at this time, only that portion of the insulating film 104b which lies under the opening of the stopper 113 is removed.
Subsequently, an Al film 114 is formed on the entire surface as shown in FIG. 2D by a known method like sputtering.
Then, the Al film 114 is polished and removed by CMP, yielding a groove interconnection structure which has the Al-filled interlayer contact hole 105 and an Al-filled groove pattern, as shown in FIG. 2E.
(c) Third Conventional Semiconductor Devices
Another known conventional semiconductor device is described in "Proceedings of 1993 VLSI Multilevel Interconnection Conference, pp. 15-21 (1993)" (hereinafter called the "third prior art example"). This third prior art example will now be discussed with reference to FIGS. 3A to 3E, which are vertical cross-sectional views illustrating the fabrication process for this example.
According to the third prior art example, as shown in FIG. 3A, first, an insulating film 104a of PI 5180 (polyimide resin) is formed 500 to 1000 nm thick on a silicon substrate 101 by rotational coating.
Next, a stopper 113 is formed of a silicon nitride film on the top of this insulating film 104a by a plasma CVD technique.
Then, a photoresist 116 to be an etching mask is formed in a predetermined region as shown in FIG. 3B using a lithography technique.
As shown in FIG. 3C, the stopper 113 and the insulating film 104a are etched by reactive ion etching using this photoresist 114 as a mask, forming a groove pattern for interconnection. Then, the photoresist 116 is removed.
Next, as shown in FIG. 3D, a tantalum film (Ta film) 106a is formed by sputtering, followed by the formation of a copper film (Cu film) 109a on the Ta film 106a to bury the interconnection groove pattern.
Then, as shown in FIG. 3E, the Cu film 109a and the Ta film 106a are removed by a known CMP process called "Damascene process " in such a way that the Cu film 109a and Ta film 106a remain only inside the interconnection groove pattern. At this time, the stopper 113 serves as a stopper layer in the polishing step because the polishing speed of the stopper 113 on the insulating film 104a is slower than those of the Cu film 109a and Ta film 106a.
According to the third prior art example, a semiconductor device having an interconnection whose main conductive layer is made of Cu is fabricated through those steps A to E.
(d) Fourth Conventional Semiconductor Devices
A further known conventional semiconductor device is described in Unexamined Japanese Patent Publication No. Sho 63-207153 (hereinafter called the "fourth prior art example"). This example will now be discussed with reference to FIGS. 4A to 4F which are vertical cross-sectional views illustrating the fabrication process consisting of steps 4A to 4B.
According to the fourth prior art example, as shown in FIG. 4A, an insulating film 104a constituted of a silicon dioxide film is formed on a silicon substrate (not shown).
Subsequently, an underlying Al interconnection 112 of 1.0 .mu.m in thickness is formed using a known technique, and an insulating film 104b constituted of a PSG film with a thickness of 1.0 to 1.5 .mu.m is formed on the entire surface of the resultant structure.
Then, an upper lying Al interconnection 115 having a thickness of 1.0 .mu.m is formed on the insulating film 104b as shown in FIG. 4B.
Next, as shown in FIG. 4C, a stopper 113 made of a silicon nitride film of 200 nm thick is formed on the entire surface of the resultant structure by a plasma CVD technique.
Subsequently, the stopper 113, the upper lying Al interconnection 115 and the insulating film 104b are partially removed using a resist (not shown) as an etching mask to form an interlayer contact hole 105 in the portion where the underlying Al interconnection 112 crosses the upper lying Al interconnection 115, as shown in FIG. 4D.
Single positioning is sufficient for opening this hole, and the opening need not be made particularly narrow and should have a diameter about the same as the widths of those interconnections. Therefore, the precision of the positioning need not be particularly high.
Next, an Al film 114 is formed 2000 to 3000 nm thick by downflow vapor deposition, as shown in FIG. 4E.
Then, the Al film 114 on the stopper 113 is polished out, yielding a structure with the Al film 114 buried in the interlayer contact hole 105, as shown in FIG. 4F.
The first to fourth prior art examples have the following shortcomings.
For the first prior art example (the semiconductor device disclosed in U.S. patent application Ser. No. 4,789,648), the point of exposure of the insulating film 104a in the CMP process is the end of the polishing (see FIG. 1B). It is therefore easy to detect the end by a change in electric capacitance.
The interconnection itself has a single-layer structure of Al (Al film 114 or Al alloy) so that a contact with the same kind of metal is made at the interlayer contact portion, resulting in a low contact resistance. But, this first prior art example suffers poor durability with respect to electromigration and stress migration.
The interconnection itself of the first prior art example cannot therefore have high and continuing reliability.
Even if one tries to use a metal, such as Cu or Au, which has a high conductivity and high durability with respect to the electromigration and stress migration to overcome this problem, those metals are difficult to use due to their reaction with silicon dioxide film and their adhesion to insulating film.
For the second prior art example (the semiconductor device disclosed in U.S. patent application Ser. No. 4,944,836), like the first prior art example, the point of exposure of the insulating film in the metal CMP process is the end of the polishing. It is therefore easy to detect the end by a change in electric capacitance.
While the interconnection itself has a single-layer structure of Al film or Al alloy so that a contact with the same kind of metals is made at the interlayer contact portion, resulting in a low contact resistance, this second prior art example suffers poor durability with respect to electromigration and stress migration as per the first prior art example.
In the second prior art example, metal like Cu which reacts with the silicon dioxide film or Au which has poor adhesion with the insulating film cannot be used as an interconnection material.
Further, the structure and process of this example are such that although the stopper used in the polishing process is Al.sub.2 O.sub.3 having a high dielectric constant (see "the stopper 113 formed of Al.sub.2 O.sub.3 " in FIG. 2A), it remains after the formation of the interconnection, thus increasing the interlayer capacitance. This results in lower electrical performance.
The third prior art example employs such an interconnection structure that the Ta film 106a protects the Cu film 109a (see FIG. 3E), thus ensuring a high durability with respect to electromigration and stress migration.
Further, when Ta as a barrier metal is also removed by polishing, it is easy to detect the end of the polishing.
According to the third prior art example, however, when the interconnection takes a multilevel structure, the interlayer contact hole portion provides a contact with different metals, namely, Cu as a conductive film lying over the lower multilevel interconnection and Ta as a conductive film underlying the upper multilevel interconnection. As a result, the contact resistance becomes higher than the case of the Cu--Cu contact, also increasing the overall electric resistance of the multilevel interconnection, so that the obtained semiconductor device does not have good electrical characteristics.
To form the structure that provides a contact with the same kind of metal at the interlayer contact portion, it is necessary to leave the Ta film 106a in the polishing process and then form the Cu film 109a thereon to provide the interconnection in the third prior art example (see FIGS. 3D and 3E). With Ta left as in this case, the end of the polishing cannot be detected.
In the fourth prior art example (the semiconductor device disclosed in Unexamined Japanese Patent Publication No. Sho 63-207153), the point of exposure of the insulating film in the CMP process for the metal film is the end of the polishing, so that it is easy to detect the end by a change in electric capacitance.
As in the first and second prior art examples, however, the interconnection itself has a single-layer structure of Al (Al film 114 or Al alloy) (see FIG. 4F). While the same kind of metals contact with each other at the interlayer contact portion, resulting in a low contact resistance, this fourth prior art example also suffers poor durability with respect to electromigration and stress migration.
In the fourth prior art example, at the time of forming the interlayer contact hole, a hole of approximately the same width as the interlayer contact hole is formed so that the opening need not be made particularly narrow (see FIG. 4D). If positioning with the positioning pattern is inaccurate, however, the insulating film on the sides of the underlying interconnection is etched so that this etched portion is also filled with metal.
When fine interconnections with a small positioning margin and a narrow interconnection pitch are to be formed, shorting between the interconnections is likely to occur, thus making it difficult to adapt this example to a semiconductor device which has fine design rules.
Further, the structure and process of this fourth example are such that a silicon nitride film having a high dielectric constant is used as the stopper 113 in the polishing process and the stopper 113 remains after the formation of the interconnection (see FIG. 4F), thus increasing the interlayer capacitance. The resultant semiconductor device does not have excellent electric characteristics.